1. Field of the Invention
The present invention relates to the field of memories and, particularly, to sense amplifiers for a memory array.
2. Description of Related Art
Sense amplifiers are used to detect small differential signals generated by memory cells and to shift the voltage levels of the memory cell output signals to a magnitude compatible with the other output circuitry in a memory chip. Smallest possible transistors are incorporated in the memory array to make memory chips cost-effective. Memory cell sizes and the corresponding memory cell output signals are reduced as array density is increased to maintain cost effectiveness. As a result, sense amplifiers are required to be very sensitive to small differences in input signals coming from the memory cells, be as fast as possible, and not consume a large portion of layout area.
Conventionally, small memory cell signals are detected with a differential amplifier. A prior art differential amplifier 15 is shown in FIG. 1. Transistors T1 and T2 form the differential input pair receiving input signals from the memory cells. Transistor T3 is used to enable and bias amplifier 15. A reference voltage generator 12 is used to increase the differential amplifier's sensitivity to changes in input differential by maintaining an optimum voltage at the common node (10) of differential input pair T1 and T2. Supply currents I1 and I2 are generated in a variety of fashions, but most typically with two transistors in a current mirror arrangement. Although this circuit is relatively fast, reference voltage generator 12 used to bias amplifier 15 uses chip current, is sensitive to process variations, and uses additional chip area. In addition, amplifier 15 itself has a relatively low gain.
Another prior art amplifier configuration shown in FIG. 2 eliminates reference voltage generator 12 by using a dual current mirror differential arrangement to split the supply current into "drive" paths 21 and 22 as well as "reference" paths 23 and 24. In this manner, amplifier 25 is self-biased. This type of amplifier shown in FIG. 2 is relatively stable over process variations, is sensitive to small input signal levels, but still requires a sizable layout area and has a relatively low gain. Additional differential sense stages are often required to buffer output signals 28 and 29 to levels where conventional CMOS logic can be effectively used. Until the sensed levels are buffered to near supply rail values, the subsequent circuitry in the critical path uses DC power.